Example System Implementation
Example System Implementation
CorePCIF provides an extremely flexible PCI interface that can be configured in many ways. Figure 1-4 shows a PCI-
to-1553 interface. In this example, CorePCIF is configured as a Target with a single memory BAR used to access the
Core1553BRT memory.
PCI Bus
CorePCIF
Dual Port
Memory
Core1553BRT
1553B
Busses
Figure 1-4 · Simple Target Implementation
A more complex system is shown in Figure 1-5 . In this case, the core supports both Target and Master operation.
Core8051 is connected to the backend interface, allowing it to initiate PCI cycles. Core8051 is used to control the AES
encryption core and the Core10/100 Ethernet interface. CorePCIF has two memory BARs configured. The first allows
the PCI interface to access the 8051 memory space, and the second reads data from the FIFO.
PCI Bus
CorePCIF
Core8051
Memory
FIFO
CoreAES
Core10/100
Ethernet
Figure 1-5 · Master and Target Implementation
v4.0
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相关PDF资料
COREU1LL-AR IP MODULE COREU1LL
COREU1PHY-AR IP MODULE COREU1PHY
CORR-8BIT-XM-UT2 SITE LICENSE IP CORRELATOR XP
CP2-GSA-L CONN SHIELD LOWER TYPE A 22
CP2-HSA110-1 CONN SHROUD CPCI 2MM TYPE A 22
CP2-HSC055-4 CONN SHROUD CPCI 2MM TYPE C 11
CP2-K3567-SR-F COMPACT PCI - MISC
CP2105EK KIT EVAL FOR CP2105
相关代理商/技术参数
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